1. Field of the Invention
This invention relates generally to computer processors and, more particularly, to computer processors with buffer storage between the processor core and main memory.
2. Description of the Related Art
Computer processors execute machine instructions specified by operation codes, generally referred to as "opcodes", and operands to carry out programming steps specified by a compiler or assembler. Frequently, the machine instruction references one or more data values that are used as the operand in an arithmetic operation, a memory transfer operation, a branch instruction to another machine instruction, and the like. Typically, the referenced data value can be found in either memory (perhaps buffered by intermediate storage such as a cache) or in addressable registers. Each type of data storage has benefits and drawbacks.
Memory locations are accessed by specifying a memory location address where a data value is stored. Memory locations are useful for storing large blocks of data and numerically large data values and are compatible with a variety of addressing schemes. Memory locations arc especially useful for accommodating variable data record storage requirements. That is processors often must access data records that comprise collections of objects of varying length. With memory locations, data objects of varying length are simply referenced by the corresponding memory addresses.
Although memory locations provide great flexibility, the access times for memory locations are among the slowest within the memory hierarchy and are not particularly stable from access operation to access operation. The variation in access time is due primarily to the way in which spatial and temporal locality within the address reference sequence (trace) interacts with any caching, interconnect, and memory banking organizations present within the processor. Finally, a relatively large number of bits can be required to encode memory location references because the memory location addresses can be quite lengthy. For example, the result of an effective address computation is thirty-two bits or more for most modern processors, compared with three to five bits typically used to designate a register.
Registers access data much faster as compared to memory locations. This is due in part to the hardware design of the logic gates that implement registers. The fast access time also is due in part to the simplified addressing scheme of registers. Typically, registers are referenced by a short register name. In this way, the entire contents of a thirty-two bit register might be accessed using only the bits required for the opcode and a four-bit name character.
Unfortunately, registers are more expensive to provide in a processor than are memory locations, again because of the hardware design and logic circuitry. Therefore, most processors have a limited number of registers. In addition, the number of registers is limited by the register addressing scheme, which is restricted but highly efficient. Finally, some values cannot be kept in registers because of what is known as the ambiguous reference problem. The ambiguous reference problem occurs when a variable, such as a cell in an array or a pointer, can be known by more than one name. For example, if a sequence of machine instructions refers to two names called x and y, and if one of them is a data value and the other is a pointer, or if both are cells in an array, then both x and y might refer to the same data object, although they appear to reference two different objects. Thus, one name is really an alias for the other.
At compile time, if a compiler can distinguish between the two names, then the data objects x and y can be kept in two different registers. On the other hand, if the compiler can determine that the two names always refer to the same data object, then both names can be mapped to the same register. If the compiler cannot determine if the two names either always or never refer to the same object, then x and y are said to be ambiguously referenced, or related, to each other. If two names are ambiguously referenced to each other, then generally they cannot be kept in registers for any length of time.
A data cache is a small, relatively high-speed memory containing copies of values addressed associatively by main memory addresses. If an instruction references a memory location, the data cache can be checked to determine if the referenced memory location is mapped into the data cache. If it is, then the referenced value is contained in the data cache and there is no need to go to the memory to obtain the value.
Recently, cache-registers (generally called "C-registers" or "C-regs") have been proposed that can be addressed in register-like fashion with short names. Thus, an opcode might specify a C-reg store into "0", which would result in a store operation into the cache register numbered zero. As with conventional registers, such a reference is much more efficient than specifying an entire memory address location. Unlike conventional registers, however, C-regs can be used even if two data object names are ambiguously aliased to each other. Each C-reg holds both an address and a data value. When a C-reg is referenced, an associative search is made by appropriate processor blocks to find neighboring C-regs that have the same address in their address field. Any C-regs found in this way are alternative names for the directly named C-reg, and the C-reg hardware simply maintains coherence of such entries. Unfortunately, C-regs provide only fixed length storage, like conventional registers, and therefore are not as compatible with varying data record storage requirements as memory locations.
From the discussion above, it should be apparent that there is a need for a processor that permits addressing data records with greater efficiency than memory locations and with more deterministic access times, eliminates the ambiguous reference problem, and provides greater storage flexibility than the fixed length storage of conventional hardware registers and cache registers. The present invention satisfies this need.